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| (R) ISL8009A Data Sheet February 13, 2008 FN6656.0 1.5A Low Quiescent Current 1.6MHz High Efficiency Synchronous Buck Regulator The ISL8009A is a high efficiency, monolithic, synchronous step-down DC/DC regulator that can deliver up to 1.5A continuous output current. It is optimized for generating low output voltages down to 0.8V. The supply voltage range of 2.7V to 5.5V, allows the use of single Li+cell, three NiMH cells or a regulated 5V input. The ISL8009A uses current mode control architecture to deliver very low duty cycle operation at high frequency with fast transient response and excellent loop stability. It has flexible operation mode selection of forced PWM mode and automatic PFM/PWM with as low as 17A quiescent current, achieving high power conversion efficiency under light load condition, hence maximizing battery life. High 1.6MHz pulse-width modulation (PWM) switching frequency allows the use of small external components. The ISL8009A integrates a pair of low ON-resistance P-Channel and N-Channel internal MOSFETs to maximize efficiency and minimize external component count. The 100% duty-cycle operation allows less than 400mV dropout voltage at 1.5A output current. The ISL8009A offers a 2ms Power-On-Reset (POR) timer at power-up. The timer output can be reset by RSI. When shutdown, ISL8009A discharges the output capacitor through a 100 resistor. Other features include internal digital soft-start, enable for power sequence, overcurrent protection, and thermal shutdown. The ISL8009A is offered in a 2mmx3mm 8 Ld DFN package with 1mm maximum height. The complete converter occupies less than 1cm2 area. Features * High Efficiency Synchronous Buck Regulator with up to 95% Efficiency * 2ms Reset Timer * 2.7V to 5.5V Supply Voltage * 3% Output Accuracy Over-Temperature/Load/Line * 1.5A Guaranteed Output Current * 17A Quiescent Supply Current in PFM Mode * Selectable Forced PWM Mode and PFM Mode * Less Than 1A Logic Controlled Shutdown Current * 90% Maximum Duty Cycle for Lowest Dropout at 1.5A * Internal Current Mode Compensation * Internal Digital Soft-Start * Peak Current Limiting, Short Circuit Protection * Over-Temperature Protection * Enable * Soft Discharge Disable * Small 8 Ld 2mmx3mm DFN * Pb-Free (RoHS Compliant) Applications * DC/DC POL Modules * C/P, FPGA and DSP Power * Plug-in DC/DC Modules for Routers and Switchers * Portable Instruments * Test and Measurement Systems Ordering Information PART NUMBER (Note) ISL8009AIRZ-T* TEMP. RANGE PART (C) MARKING 09A PACKAGE (Pb-free) PKG. DWG. # Pinout ISL8009A (8 LD DFN) TOP VIEW -40 to +85 8 Ld 2x3 DFN L8.2x3 *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. VIN EN POR SKIP 1 2 3 4 8 7 6 5 LX GND VFB RSI 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL8009A Absolute Maximum Ratings (Reference to GND) Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V EN, RSI, SKIP, VFB, POR . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V LX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V to 6.5V VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V Thermal Information Thermal Resistance (Typical, Notes 1, 2) JA (C/W) JC (C/W) 8 Ld 2x3 DFN Package . . . . . . . . . . 65 6 Junction Temperature Range. . . . . . . . . . . . . . . . . .-55C to +125C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 1.5A Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40C to +85C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 3. Limits established by characterization and are not production tested. Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specifications are measured at the following conditions: TA = +25C, EN = VIN, RSI = SKIP = 0V, VIN = 5V, L = 2.2H, C1 = C2 = 20F, IOUT = 0A to 1.5A, unless otherwise noted. See "Typical Applications" on page 8. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS PARAMETER INPUT SUPPLY VIN Undervoltage Lockout Threshold VUVLO Rising Falling 2.2 - 2.5 2.4 17 15 3.7 0.1 2.7 30 6 2 V V A A mA A Quiescent Supply Current IVIN SKIP = VIN, no load at the output SKIP = VIN, no load at the output and no switches switching, design info only SKIP = GND, no load at the output Shutdown Supply Current OUTPUT REGULATION VFB Regulation Voltage VFB Bias Current Output Voltage Accuracy Line Regulation COMPENSATION Error Amplifier Trans-Conductance LX P-Channel MOSFET ON-Resistance ISD VIN = 5.5V, EN = low VVFB IVFB VFB = 0.75V VIN = VO + 0.5V to 5.5V, IO = 0A to 1A (Note 3) VIN = VO + 0.5V to 5.5V (minimal 2.7V) 0.784 -3 - 0.8 0.1 0.2 0.816 3 - V A % %/V Adjustable version, design info only - 20 - A/V VIN = 5.5V, IO = 200mA VIN = 2.7V, IO = 200mA 1.8 0.12 0.16 0.11 0.15 2.1 1.6 70 1.1 0.22 0.27 0.22 0.27 2.6 1.75 100 - A % MHz ns ms N-Channel MOSFET ON-Resistance VIN = 5.5V, IO = 200mA VIN = 2.7V, IO = 200mA P-Channel MOSFET Peak Current Limit LX Maximum Duty Cycle PWM Switching Frequency LX Minimum On-Time Soft-Start-Up Time IPK IO = 1.5A fS SKIP = low (forced PWM mode) 90 1.35 - 2 FN6656.0 February 13, 2008 ISL8009A Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specifications are measured at the following conditions: TA = +25C, EN = VIN, RSI = SKIP = 0V, VIN = 5V, L = 2.2H, C1 = C2 = 20F, IOUT = 0A to 1.5A, unless otherwise noted. See "Typical Applications" on page 8. (Continued) SYMBOL Enable = 0 TEST CONDITIONS MIN 80 TYP 100 MAX 120 UNITS PARAMETER Soft-Discharge Resistor POR Output Low Voltage Delay Time POR Pin Leakage Current Minimum Supply Voltage for Valid POR Signal Internal PGOOD Low Rising Threshold Internal PGOOD Low Falling Threshold Internal PGOOD High Rising Threshold Internal PGOOD High Falling Threshold Internal PGOOD Delay Time EN, SKIP, RSI Logic Input Low Logic Input High Logic Input Leakage Current Thermal Shutdown Thermal Shutdown Hysteresis Sinking 1mA, VFB = 0.7V - 2 0.01 92 88 112 107 50 0.3 0.1 94.5 91 114 110 - V ms A V % % % % s POR = VIN = 3.6V 1.2 Percentage of nominal regulation voltage Percentage of nominal regulation voltage Percentage of nominal regulation voltage Percentage of nominal regulation voltage 89.5 85 108 104 - 1.4 Pulled up to 5.5V - 0.1 140 25 0.4 1 - V V A C C Pin Descriptions VIN Input supply voltage. Connect a 10F ceramic capacitor to power ground. VFB Buck regulator output feedback. Connect to the output through a resistor divider for adjustable output voltage (ISL8009A-ADJ). For preset output voltage, connect this pin to the output. EN Regulator enable pin. Enable the output when driven to high. Shutdown the chip and discharge output capacitor when driven to low. Do not leave this pin floating. RSI This input resets the 2ms timer. When the output voltage is within the PGOOD window, an internal timer is started and generates a POR signal 2ms later when RSI is low. A high RSI resets POR and RSI high to low transition restarts the internal counter if the output voltage is within the window, otherwise the counter is reset by the output voltage condition. POR 2ms timer output. At power-up or EN HI, this output is a 2ms delayed Power-Good signal for the output voltage. This output can be reset by a low RSI signal. 2ms starts when RSI goes to high. Exposed Pad The exposed pad must be connected to the GND pin for proper electrical performance. The exposed pad must also be connected to as much as possible for optimal thermal performance. SKIP Mode Selection pin. Connect to logic high or input voltage VIN for PFM mode; connect to logic low or ground for forced PWM mode. Do not leave this pin floating. LX Switching node connection. Connect to one terminal of inductor. GND System ground. 3 FN6656.0 February 13, 2008 ISL8009A Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25C, VVIN = 5V, EN = VIN, RSI = SKIP = 0V, L = 2.2H, C1 = 20F, C2 = 20F, IOUT = 0A) 100 90 80 EFFICIENCY (%) 1.5VOUT - PWM EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.00 0.25 0.50 0.75 1.00 1.25 1.50 40 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 1.2VOUT - PWM 2.5VOUT - PWM 1.8VOUT - PWM 90 80 70 60 50 1.2VOUT - PFM 2.5VOUT - PFM 1.5VOUT - PFM 1.8VOUT - PFM 100 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 1. EFFICIENCY vs LOAD, VIN = 3.3V PWM FIGURE 2. EFFICIENCY vs LOAD, VIN = 3.3V PFM 100 90 80 EFFICIENCY (%) EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.2VOUT - PWM 1.5VOUT - PWM 2.5VOUT - PWM 1.8VOUT - PWM 3.3VOUT - PWM 100 90 80 70 60 50 40 0.05 1.2VOUT - PFM 1.5VOUT - PFM 2.5VOUT - PFM 3.3VOUT - PFM 1.8VOUT - PFM 0.15 0.25 0.35 0.45 0.55 0.65 0.75 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 3. EFFICIENCY vs LOAD, VIN = 5V PWM FIGURE 4. EFFICIENCY vs LOAD, VIN = 5V PFM 1.24 1.23 OUTPUT VOLTAGE (V) 2.8VIN - PWM 1.22 1.21 1.20 1.19 1.18 1.17 1.16 0.00 0.25 0.50 0.75 1.00 OUTPUT LOAD (A) 1.25 1.50 3.3VIN - PWM 2.8VIN - PFM 3.3VIN-PFM 5VIN - PWM 5VIN - PFM OUTPUT VOLTAGE (V) 1.54 1.53 1.52 2.8VIN - PWM 1.51 1.50 1.49 1.48 1.47 1.46 0.00 0.25 0.50 0.75 1.00 1.25 1.50 3.3VIN - PWM 2.8VIN - PFM 3.3VIN-PFM 5VIN - PWM 5VIN - PFM OUTPUT LOAD (A) FIGURE 5. VOUT REGULATION vs LOAD, VOUT = 1.2V FIGURE 6. VOUT REGULATION vs LOAD, VOUT = 1.5V 4 FN6656.0 February 13, 2008 ISL8009A Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25C, VVIN = 5V, EN = VIN, RSI = SKIP = 0V, L = 2.2H, C1 = 20F, C2 = 20F, IOUT = 0A) (Continued) 1.84 1.83 OUTPUT VOLTAGE (V) 1.82 1.81 2.7VIN - PWM 1.80 1.79 1.78 1.77 1.76 0.00 4VIN - PWM 2.7VIN - PFM 4VIN-PFM OUTPUT VOLTAGE (V) 5.5VIN - PWM 5.5VIN - PFM 2.54 2.53 2.52 2.51 2.50 2.49 2.48 2.47 1.25 1.50 2.46 0.00 0.25 0.50 0.75 1.00 OUTPUT LOAD (A) 1.25 1.50 3.3VIN - PFM 3.3VIN - PWM 5VIN - PWM 5VIN - PFM 0.25 0.50 0.75 1.00 OUTPUT LOAD (A) FIGURE 7. VOUT REGULATION vs LOAD, VOUT = 1.8V FIGURE 8. VOUT REGULATION vs LOAD, VOUT = 2.5V 3.42 3.40 OUTPUT VOLTAGE (V) 3.38 3.36 3.34 3.32 3.30 3.28 3.26 0.00 0.25 0.50 0.75 1.00 OUTPUT LOAD (A) 1.25 1.50 4VIN - PFM 3.3VIN - PWM 5VIN-PFM 4VIN - PWM 5.5VIN - PWM 5.5VIN - PFM 0.7 2.8VIN - PWM POWER DISSIPATION (W) 0.6 0.5 0.4 0.3 2.8VIN - PFM 0.2 0.1 0.0 0.00 3.3VIN - PWM 5VIN - PWM 5VIN - PFM 0.25 0.50 0.75 1.00 OUTPUT LOAD (A) 1.25 1.50 3.3VIN-PFM FIGURE 9. VOUT REGULATION VS LOAD, VOUT = 3.3V FIGURE 10. POWER DISSIPATION vs LOAD, 1.6 MHz, VOUT = 1.8V 45 40 POWER DISSIPATION (mW) OUTPUT VOLTAGE (V) 35 30 25 20 15 10 5 0 2.75 3.25 3.75 4.25 VIN (V) 4.75 5.25 NO LOAD - PFM NO LOAD- PWM 2.5 0.75A LOAD 2.0 1.5 1.5A LOAD 1.0 NO LOAD 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 INPUT VOLTAGE (V) FIGURE 11. POWER DISSIPATION vs VIN AT NO LOAD, VOUT = 1.8V FIGURE 12. OUTPUT VOLTAGE REGULATION vs VIN PWM MODE 5 FN6656.0 February 13, 2008 ISL8009A Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25C, VVIN = 5V, EN = VIN, RSI = SKIP = 0V, L = 2.2H, C1 = 20F, C2 = 20F, IOUT = 0A) (Continued) 2.0 NO LOAD OUTPUT VOLTAGE (V) 1.5 1.0 0.75A LOAD 1.5A LOAD LX 2V/DIV VOUT RIPPLE 20mV/DIV 0.5 0.0 -0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 IL 0.2A/DIV INPUT VOLTAGE (V) FIGURE 13. OUTPUT VOLTAGE REGULATION vs VIN SKIP MODE FIGURE 14. STEADY STATE OPERATION AT NO LOAD (PWM), 1s/DIV LX 2V/DIV LX 2V/DIV VOUT RIPPLE 20mV/DIV IL 0.5A/DIV IL 0.2A/DIV VOUT RIPPLE 20mV/DIV FIGURE 15. STEADY STATE OPERATION AT NO LOAD (PFM), 1s/DIV FIGURE 16. STEADY STATE OPERATION WITH FULL LOAD, 1s/DIV LX 2V/DIV LX 2V/DIV VOUT RIPPLE 50mV/DIV IL 1A/DIV IL 1A/DIV VOUT RIPPLE 50mV/DIV FIGURE 17. LOAD TRANSIENT (PWM), 200s/DIV FIGURE 18. LOAD TRANSIENT (PFM), 200s/DIV 6 FN6656.0 February 13, 2008 ISL8009A Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25C, VVIN = 5V, EN = VIN, RSI = SKIP = 0V, L = 2.2H, C1 = 20F, C2 = 20F, IOUT = 0A) (Continued) EN 2V/DIV VOUT 1V/DIV EN 2V/DIV VOUT 0.5V/DIV IL 1A/DIV IL 1A/DIV POR 2V/DIV POR 1V/DIV FIGURE 19. SOFT-START AT NO LOAD, 500s/DIV FIGURE 20. SOFT-START WITH PRE-BIASED 1V, 500s/DIV LX 2V/DIV EN 2V/DIV VOUT 0.5V/DIV IL 0.5A/DIV IL 1A/DIV VOUT 1V/DIV POR 2V/DIV POR 5V/DIV FIGURE 21. SOFT-START AT FULL LOAD, 500s/DIV FIGURE 22. OUTPUT SHORT CIRCUIT, 10.0s/DIV VOUT 1V/DIV IL 1A/DIV POR 5V/DIV FIGURE 23. OUTPUT SHORT CIRCUIT RECOVERY, 500s/DIV 7 FN6656.0 February 13, 2008 ISL8009A Typical Applications L 2.2H VIN C1 20F ISL8009A EN R1 100k POR VFB R3 100k LX C2 20F GND R2 124k OUTPUT 1.8V TO 1.5A INPUT 2.7V TO 5.5V SKIP RSI FIGURE 24. TYPICAL APPLICATION DIAGRAM Block Diagram SKIP SHUTDOWN SOFT- START SHUTDOWN 27pF 390k EN BANDGAP VFB SLOP SLOPE E COMP COMP 0.864V 0.736V + SKIP POR 2ms DELAY RSI 0.2V 8 + + 0.8V EAMP OSCILLATOR + COMP PWM/PFM LOGIC CONTROLLER PROTECTION DRIVER VIN LX + GND + CSA1 + OCP + 0.85V 0.17V ZERO - CROSS SENSING SCP + FIGURE 25. FUNCTIONAL BLOCK DIAGRAM FN6656.0 February 13, 2008 ISL8009A Theory of Operation The ISL8009A is a step-down switching regulator optimized for battery-powered handheld applications. The regulator operates at 1.6MHz fixed switching frequency under heavy load condition to allow small external inductor and capacitors to be used for minimal printed-circuit board (PCB) area. At light load, the regulator reduces the switching frequency, unless forced to the fixed frequency to minimize the switching loss and to maximize the battery life. The quiescent current when the output is not loaded is typically only 17A. The supply current is typically only 0.1A when the regulator is shutdown. The output voltage is regulated by controlling the reference voltage to the current loop. The bandgap circuit outputs a 0.8V reference voltage to the voltage control loop. The feedback signal comes from the VFB pin. The soft-start block only affects the operation during the start-up and will be discussed separately. The error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. The voltage loop is internally compensated with the 30pF and 300k RC network. The maximum EAMP voltage output is precisely clamped to the bandgap voltage (1.172V). VEAMP VCSA1 Duty DUTY Cycle CYCLE IL PWM Control Scheme The ISL8009A employes the current-mode pulse-width modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting. Figure 25 shows the block diagram. The current loop consists of the oscillator, the PWM comparator COMP, the current sensing circuit, and the slope compensation for the current loop stability. The current sensing circuit consists of the resistance of the P-Channel MOSFET when it is turned on and the current sense amplifier CSA. The gain for the current sensing circuit is typically 0.4V/A. The control reference for the current loops comes from the error amplifier EAMP of the voltage loop. The PWM operation is initialized by the clock from the oscillator. The P-Channel MOSFET is turned on at the beginning of a PWM cycle and the current in the MOSFET starts to ramp up. When the sum of the current amplifier CSA and the compensation slope (0.675V/s) reach the control reference of the current loop, the PWM comparator COMP sends a signal to the PWM logic to turn off the P-MOSFET and to turn on the N-Channel MOSFET. The N-MOSFET stays on until the end of the PWM cycle. Figure 26 shows the typical operating waveforms during the PWM operation. The dotted lines illustrate the sum of the compensation ramp and the current-sense amplifier CSA output. VOUT FIGURE 26. PWM OPERATION WAVEFORMS SKIP Mode The ISL8009A enters a pulse-skipping mode at light load to minimize the switching loss by reducing the switching frequency. Figure 27 illustrates the skip-mode operation. A zero-cross sensing circuit shown in Figure 25 monitors the N-MOSFET current for zero crossing. When 8 consecutive cycles of the N-MOSFET crossing zero are detected, the regulator enters the skip mode. During the 8 detecting cycles, the current in the inductor is allowed to become negative. The counter is reset to zero when the current in any cycle does not cross zero. CLOCK Clock 88 Cycles CYCLES CURRENTLimit Current LIMIT IL 0 NOMINAL 1.5% Nominal ++1.5% LOAD CURRENT Load Current VOUT NOMINAL Nominal FIGURE 27. SKIP MODE OPERATION WAVEFORMS 9 FN6656.0 February 13, 2008 ISL8009A Once the skip mode is entered, the pulse modulation starts being controlled by the SKIP comparator shown in Figure 25. Each pulse cycle is still synchronized by the PWM clock. The P-MOSFET is turned on at the clock and turned off when its current reaches 20% of the current limit value (0.2V at the CSA output). As the average inductor current in each cycle is higher than the average current of the load, the output voltage rises cycle over cycle. When the output voltage reaches 1.5% above the nominal voltage, the P-MOSFET is turned off immediately and the inductor current is fully discharged to zero and stays at zero. The output voltage reduces gradually due to the load current discharging the output capacitor. When the output voltage drops to the nominal voltage, the P-MOSFET will be turned on again at the clock, repeating the previous operations. The regulator resumes normal PWM mode operation when the output voltage drops 1.5% below the nominal voltage. . VO RSI 2ms POR MIN 25ns 2ms FIGURE 28. RSI AND POR TIMING DIAGRAM UVLO When the input voltage is below the undervoltage lock out (UVLO) threshold, the regulator is disabled. Soft-Start-Up The soft start-up eliminates the in-rush current during the start-up. The soft-start block outputs a ramp reference to both the voltage loop and the current loop. The two ramps limit the inductor current rising speed as well as the output voltage speed so that the output voltage rises in a controlled fashion. At the very beginning of the start-up, the output voltage is less than 0.2V; hence the PWM operating frequency is 1/3 of the normal frequency. Mode Control The ISL8009A has a SKIP pin that controls the operation mode. When the SKIP pin is driven to low or shorted to ground, the regulator operates in a forced PWM mode. The forced PWM mode remains the fixed PWM frequency at light load instead of entering the skip mode. Overcurrent Protection The overcurrent protection is realized by monitoring the CSA output with the OCP comparator, as shown in Figure 25. The current sensing circuit has a gain of 0.4V/A, from the N-MOSFET current to the CSA output. When the CSA output reaches 0.8V, (which is equivalent to 2A for the switch current) the OCP comparator is tripped to turn off the P-MOSFET immediately. Power MOSFETs The power MOSFETs are optimized for best efficiency. The ON-resistance for the P-MOSFET is typically 120m and the ON-resistance for the N-MOSFET is typically 110m. Duty Cycle The ISL8009A features duty cycle operation to maximize the battery life. When the battery voltage drops to a level that the ISL8009A can no longer maintain the regulation at the output, the regulator completely turns on the P-MOSFET. The maximum drop out voltage under the duty-cycle operation is the product of the load current and the ON-resistance of the P-MOSFET. Short-Circuit Protection A short-circuit protection SCP comparator monitors the VFB pin voltage for output short-circuit protection. When the VFB is lower than 0.2V, the SCP comparator forces the PWM oscillator frequency to drop to 1/3 of the normal operation value. This comparator is effective during start-up or an output short-circuit event. Enable The Enable (EN) input allows the user to control the turning on or off of the regulator for purposes such as power-up sequencing. When the regulator is enabled, there is typically a 600s delay for waking up the bandgap reference, then the soft-start-up begins. When the regulator is disabled, the P-MOSFET and the N-MOSFET are turned off immediately. The 100 soft discharge resistor from LX to GDN is activated and pulls the output to 0V. RSI/POR Function When powering up, the open-collector Power-On-Reset output holds low for about 1ms after VO reaches the preset voltage. When the active-HI reset signal RSI is issued, POR goes to low immediately and holds for the same period of time after RSI comes back to LOW. The output voltage is unaffected (refer to Figure 28). When the function is not used, connect RSI to ground and leave the pull-up resistor, R4, open at the POR pin. The POR output also serves as a 1ms delayed Power-Good signal when the pull-up resistor, R4, is installed. The RSI pin needs to be directly (or indirectly through resistor, R5) connected to ground for this to function properly. Thermal Shutdown The ISL8009A has built-in thermal protection. When the internal temperature reaches +140C, the regulator is completely shutdown. As the temperature drops to +120C, the ISL8009A resumes operation by stepping through a soft-start-up. 10 FN6656.0 February 13, 2008 ISL8009A Applications Information Output Inductor and Capacitor Selection To consider steady state and transient operation, ISL8009A typically uses a 3.3H output inductor. Higher or lower inductor values can be used to optimize the total converter system performance. For example, for higher output voltage 3.3V application, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased. The inductor ripple current can be expressed in Equation 1: VO V O * 1 - --------- V IN I = -------------------------------------L * fS Output Voltage Setting Resistor Selection The resistors R2 and R3 shown in Figure 24 set the output voltage for the adjustable version. The output voltage can be calculated by Equation 2: R 2 V O = 0.8 * 1 + ------ R 3 (EQ. 2) where the 0.8V is the reference voltage. The voltage divider consists of R2 and R3 and increases the quiescent current by VO/(R2 + R3), so larger resistance is desirable. On the other hand, the VFB pin has leakage current that will cause error in the output voltage setting. The leakage current has a typical value of 0.1A. To minimize the accuracy impact on the output voltage, select the R3 no larger than 200k. For VO = 0.8V, it is recommended to short R2 and open R3. (EQ. 1) The inductor's saturation current rating needs be at least larger than the peak current. The ISL8009A protects the typical peak current 2.1A. The saturation current needs to be over 2.4A for maximum output current application. ISL8009A uses internal compensation network and the output capacitor value is dependant on the output voltage. The ceramic capacitor is recommended to be X5R or X7R. The recommended minimum output capacitor values are shown in Table 1. TABLE 1. OUTPUT CAPACITOR VALUE vs VOUT VOUT (V) 0.8 1.2 1.6 1.8 2.5 3.3 3.6 COUT (F) 10 10 10 10 10 10 10 L (H) 1.0~2.2 1.2~2.2 1.8~2.2 1.8~3.3 1.8~3.3 1.8~4.7 1.8~4.7 Layout Recommendation The layout is a very important converter design step to make sure the designed converter works well. For the ISL8009A buck converter, the power loop is composed of the output inductor L, the output capacitor COUT, the LX pin and the GND pin. It is necessary to make the power loop as small as possible. The heat of the IC is mainly dissipated through the thermal pad. Maximizing the copper area connected to the thermal pad is preferable. In addition, a solid ground plane is helpful for EMI performance. It is recommended to add 5 vias under the thermal pad connection to the solid ground plane. In Table 1, the minimum output capacitor value is given for different output voltages to make sure the whole converter system is stable. Input Capacitor Selection The main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current from flowing back to the battery rail. A 10F, X5R or X7R ceramic capacitor is a good starting point for the input capacitor selection. 11 FN6656.0 February 13, 2008 ISL8009A Dual Flat No-Lead Plastic Package (DFN) L8.2x3 8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE 2X 0.15 C A A D 2X 0.15 C B MILLIMETERS SYMBOL A A1 A3 b E MIN 0.80 - NOMINAL 0.90 0.20 REF MAX 1.00 0.05 NOTES - 0.20 0.25 2.00 BSC 0.32 5,8 - D D2 E E2 1.65 1.50 6 INDEX AREA B 1.65 3.00 BSC 1.80 0.50 BSC 1.75 7,8 - 1.90 7,8 - TOP VIEW e k // 0.10 C 0.20 0.30 0.40 8 4 0.50 8 2 3 Rev. 0 6/04 L A 0.08 C N Nd C SEATING PLANE SIDE VIEW A3 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. D2 7 8 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. NX k (DATUM B) 1 2 D2/2 6 INDEX AREA (DATUM A) 5. Dimension b applies to the metallized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. E2 E2/2 NX L N N-1 NX b 8 e (Nd-1)Xe REF. BOTTOM VIEW (A1) NX (b) 5 SECTION "C-C" CC e FOR EVEN TERMINAL/SIDE TERMINAL TIP L C L 5 0.10 M C AB All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN6656.0 February 13, 2008 |
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